1. Field of the Invention
This invention relates to a high-temperature superconducting device and a manufacturing method thereof and, more particularly, to a high-temperature superconducting device characterized by a means to form the high-temperature superconducting device by a ramp-edge-type superconductor junction with various critical current densities Jc, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, oxide high-temperature superconductors as typified by yttrium-type superconductors have been expected to be applied to various fields such as sensors and logic circuits, since their superconducting state is exhibited at a temperature higher than liquid nitrogen, suggesting that its cooling is simpler than those of the conventional metal-type superconductors which require cooling by liquid helium (refer to Japanese Patent Application Laid-open No. 2000-353831, for example).
Such oxide high-temperature superconductors have a characteristic that superconducting current thereof tends to take paths along a Cu—O plane formed of copper and oxygen in a crystal, so that it is preferable that the junction traverses along a parallel direction with respect to such a Cu—O plane. Accordingly, a ramp-edge-type junction is proposed as a superconductor junction used for a high-temperature superconducting device.
For such ramp-edge-type junctions, are known a type in which a barrier layer is formed of deposited films, and a type in which a barrier layer is formed by modifying its surface with ion implantation (refer to Japanese Patent Application Laid-open No. 2001-244511, and Supercond. Sci. Technol., Vol. 14, pp.1052–1055, 2001, for example).
Further, among superconducting circuits, a single flux quantum (SFQ) circuit has a characteristic that it is operated at an ultrahigh speed and with low energy, so that, where the SFQ circuit is designed and manufactured with the high-temperature superconductor, a superconducting loop having Josephson junction and included in a circuit has to be designed to fulfill a condition that the product of an inductance L and a critical current value Ic of the Josephson junction of the loop (product of L multiplied by Ic) is one quantum magnetic flux (Φo) or ½ Φo.
In such a case, the higher is the product of the critical current Ic and the normal conducting resistance Rn of the junction used in the SFQ circuit being the product of Ic×Rn, the narrower the width of an SFQ pulse becomes, so that a high-speed operation can be realized. An interface-modified or interface-engineered junction of the high-temperature superconductor can make the product of Ic×Rn higher by increasing an interface current density Jc, the state of which will be explained below with reference to FIG. 18.
FIG. 18 is an actual measurement data showing dependence of the product of Ic×Rn on Jc. Whilst an exponent varies depending on the state of the interface-engineered junction of the high-temperature superconductor, the following dependences are obtained:Ic×Rn=Jc0.2, orIc×Rn=Jc0.5Hence, it is understood that the product of Ic×Rn can be made larger by increasing Jc.
Here, a superconductor junction element having the interface-engineered ramp-edge junction is explained with reference to FIGS. 19A to 19C and FIGS. 20A to 20D.
First, in FIG. 19A, a YBCO (YBa2Cu3O7-x) layer 52 which serves as a lower electrode and a CeO2 film 53 which serves as an insulating layer are sequentially deposited on a SrTiO3 substrate 51 by using a pulse laser deposition method.
Next, in FIG. 19B, a photo-resist is coated, patterning is performed by exposure and development, and thereafter a reflowing process is performed, so that a resist pattern 54 is formed. Argon ion 55 is then irradiated to perform ion milling by using the resist pattern 54 as a mask, so that a ramp-edge structure is formed.
Subsequently, in FIG. 19C, a ramp slope 56 which is exposed is irradiated with argon ion 57 in such a manner that, for example, the argon ion 57 is irradiated vertically with respect to the SrTiO3 substrate 51, so that a surface-modified layer 58 is formed.
As shown in FIG. 20A, subsequently a YBCO layer 59 forming an upper electrode is deposited by using a sputtering method.
Subsequently, in FIGS. 20B to 20D, a bridge portion 60 is formed by performing ion milling to the YBCO layer 59, so that a basic structure of the interface-engineered ramp-edge junction is accomplished.
It is noted that FIG. 20B is a plain view, FIG. 20C is a schematic sectional view taken along an A–A′ dotted line in FIG. 20B, and FIG. 20D is a schematic sectional view taken along a B–B′ dotted line in FIG. 20B.
In the case described above, the ramp slopes are formed in four directions by processing the lower electrode layer, and ion is irradiated vertically with respect to the substrate surface, whereby a damage layer is formed uniformly over the ramp slopes. As a result, interface-engineered ramp-edge junctions with a uniform critical current density Jc can be formed in the four directions, so that Jc for the intra-circuit junctions can be made uniform, whereby an accurate circuit operation is realized.
As described above, in designing a SFQ circuit, the inductance L and the critical current Ic in the circuit have to be determined by fulfilling the condition for the product of L×Ic (which is L×Ic<Φo). However, in the ramp-edge structure, in which a barrier layer is sandwiched by the upper and lower electrodes through the bridge portion, parasitic inductance is generated in series with the junction.
The parasitic inductance exists in no small way, because the size of the Josephson junction or the minimum length of interval between the electrode and the wiring are determined based on a lithographic limit and constraints with respect to material processing. In such a circumstance, if Jc of the Josephson junction is made higher in order to make the product of Ic×Rn larger, the junction width, which is the bridge width, has to be narrowed so as to obtain a constant-value Ic.
In such a case, the length of the bridge which exists in series with the Josephson junction becomes longer than the width thereof, and the parasitic inductance becomes larger.
For example, in a state where the electrode thickness, bridge length, and sheet inductance respectively are constant, if a Josephson junction is fabricated in a manner that it has a constant-value critical current Ic, the critical current density Jc being made N times higher results in the junction width of 1/N times wider, and the parasitic inductance of N times larger.
Consequently, when Jc of the Josephson junction is made higher, a loop inductance of a superconducting loop containing the Josephson junction becomes larger.
Hence, the above-described condition for the product of L×Ic (L×Ic<Φo) can no longer be fulfilled, and the circuit cannot be operated.
In order to deal with such a state, in the circuit design prevailing at present, the inductance is determined in tune with a circuit whose restriction on L×Ic is the most strict among the elements in the circuit, and the junction width is widened in order to reduce the influence of the parasitic inductance as much as possible.
However, if the junction width is widened in order to reduce the parasitic inductance influence as much as possible, Jc of the Josephson junction cannot be made higher, so that the junction with relatively small-value product of Ic×Rn has to be used. Consequently, the SFQ pulse width becomes wider, and a problem is caused in which the circuit performance is deteriorated in such a manner that the operational speed of the SFQ circuit is restricted, or the operational uncertainty (jitter) becomes greater.